Tenstorrent announced this week that it has signed an agreement to license its RISC-V CPU and AI processor IP to Japan’s Leading Semiconductor Technology Center (LSTC), which will use the technology to build its edge-focused AI accelerator. The most curious part of the announcement is that the accelerator will rely on a multi-chiplet design, which will be manufactured by Japan’s Rapidus using a 2nm manufacturing process and then packaged by the same company.
Under the terms of the agreement, Tenstorrent will license its data center-grade Ascalon general-purpose processor IP to LSTC and will help implement the chiplet using Rapidus’ 2nm manufacturing process. Tenstorrent’s Ascalon is a high-performance out-of-order RISC-V CPU design with 8-wide decoding. The Ascalon core contains 6 ALUs, 2 FPUs and 2 256-bit vector units, and is expected to provide quite powerful performance when combined with 2nm process technology.
Ascalon was developed by a team led by legendary CPU designer Jim Keller, the current CEO of Tenstorrent who has been involved in successful projects at AMD, Apple, Intel and Tesla.
In addition to the general CPU IP license, Tenstorrent will co-design “chips that will redefine AI performance in Japan.” This apparently means that LSTC does not plan to license its proprietary RISC-V Tensix cores tailored for neural network inference and training, but will help design proprietary AI accelerators typically used for inference workloads.
Wei-Han Lien, chief architect of Tenstorrent RISC-V products, said: “Tenstorrent and LSTC jointly create a chiplet-based edge AI accelerator, which represents the first breakthrough attempt in cross-organizational chiplet development in the semiconductor industry.” “The edge AI accelerator will integrate LSTC’s AI chiplets and Tenstorrent’s RISC-V and peripheral chiplet technology. This pioneering strategy leverages the collective capabilities of both organizations to leverage the adaptability and efficiency of chiplet technology to meet the growing demand for AI applications. Demand. Edge.”
Rapidus aims to start producing chips using the 2nm manufacturing process currently under development in 2027, at least a year behind TSMC and a few years behind Intel. However, if mass production of 2nm begins in 2027, it will be a major breakthrough in Japan’s efforts to return to its position as a global semiconductor leader.
Building an edge AI accelerator based on Tenstorrent’s IP and Rapidus’ 2nm-class production nodes is a big deal for LSTC, Tenstorrent, and Rapidus because it validates the technology developed by these three companies.
Atsuyoshi Koike, President and CEO of Rapidus Corporation, said: “I am pleased that this collaboration is an actual project that started with the MOC agreement with Tenstorrent last November.” “We will not only cooperate on the front-end process, but also on the chiplet ( back-end process) and strive to be the leading example of our business model, enabling everything from design to back-end process in less time. Forever.”